WSL
On-Chip Calibration, Compensation, and Filtering Techniques for Wireless SoC
Time: Sunday, June 15th, 8am - 5pm
Topics & Speakers:
- IIP2 and DC offset calibration techniques in 3G transceivers, Dr. Krzysztof Dufrene, DICE Danube Integrated Circuit Engineering GmbH
- Accurate tuning and calibration of Fractional-N frequency synthesizers, Waleed Khalil, Robert Santucci, and Dmitry Petrov, Intel Corp.
- Calibration Techniques for Wireless SoCs, Arya Behzad, Broadcom Corp.
- Digital Hardware and Software Based Mechanisms for Calibration and Compensation in Wireless SoCs, Oren Eliezer, Texas Instruments
- Compensation of radio impairments for low cost wireless transceiver design, Steve Cicarrelli, Qualcomm
- Calibration, Compensation, and On-chip Filtering techniques used in 3G transceivers, Jonathan Strange, Mediatek Wireless, UK
- Digital Calibration Techniques for Cellular Receivers, Abdellatif Bellaouar, Sherif Embabi, and Hamid Safiri, Sirific Wireless
- Digital Calibration Techniques for Cellular Transmitters, Abdellatif Bellaouar, Sherif Embabi, and Hamid Safiri, Sirific Wireless
Organizers:
Dr. Walid Ali-Ahmad, MediaTek, Singapore
Sponsors: RFIC
Workshop Abstract:
As wireless SoCs are being targeted for multistandard and multi-band applications, the demand is still for excellent radio performance and minimum number of off-chip components. In addition, higher quality modulation techniques are being used in these systems to deliver higher data rates in a cellular environment. Hence, there is more weight being put on developing RF front-ends which are as good as ideal! Furthermore, there is currently a big emphasis on eliminating the undesirable large number of external RF SAW filters in multiband operation. In order to achieve all these new requirements, on-chip correction techniques are needed that complement the on-chip radio circuitry and benefit from state-of-the-art CMOS processes currently available for wireless SoCs. This workshop will review on-chip calibration techniques for RF and BB impairments compensation, plus on-chip filtering circuitry to relax front-end linearity requirements and minimize the need for off-chip filters. |